1. Field of the Invention
This invention relates to a signal charge detector of a charge transfer device such as a charge coupled device (hereinafter, referred to as a CCD), and particularly to an improvement thereof for producing output signals proportional to the values of signal charges.
2. Description of the Prior Art
A CCD linear image sensor has a line of solid-state photosensors in which charges generated in response to light irradiated thereon are accumulated, and two charge shift registers are arranged in parallel with and disposed on opposite sides of the line of solid-state photosensors. The charges accumulated in alternate photosensors are applied to one charge shift register and those accumulated in the other photosensors are applied to the other charge shift register. The charges applied to the charge shift registers are transferred in the shift registers toward first ends thereof at which a signal charge detector is formed. The transferred charges are converted into a signal of voltage form in response to their value by the signal charge detector.
The signal charge detector of the prior art has one or two sets of charge-voltage converters and MOS FET circuits. The charge-voltage converter is a P-N junction formed in a semiconductor substrate. The MOS FET circuit is a first stage amplifier receiving the converted voltage, a second stage amplifier amplifying the output of the first stage amplifier, a sampling circuit for sampling the output of the second stage amplifier, an output stage amplifier amplifying the sampled value to output an output signal and a pre-charge FET for charging the charge-voltage converter. Here, it is noted that in the case of using two FET circuits, an output stage amplifier is commonly used for the two FET circuits. First, the charge-voltage converter is charged by applying a reset pulse to the pre-charge FET. Thereafter, the transferred charges are introduced to the charge-voltage converter to apply a potential change of the charge-voltage converter to the first stage amplifier and then to the second stage amplifier. The output of the second stage amplifier is sampled in a capacitor in the sampling circuit in response to a sampling pulse. The sampled voltage signal is derived from the output stage amplifier.
The output of the signal charge detector in the prior art is affected by the gate capacitance of the pre-charge FET. When the reset pulse is applied, the charge-voltage converter is charged to a predetermined voltage. However, in response to the removal of the reset pulse, the charged voltage at the charge-voltage converter decreases by a value determined by the gate capacitance. Therefore, if two FET circuits are used in a signal charge detector, since the gate capacitances of the pre-charge FET's my deviate greatly due to uncontrollable manufacturing conditions, the output voltages from two FET circuits differs from each other.
The output of the signal charge detector of the prior art involves the signal components based on the dark current flowing in the CCD shift registers and the solid-state photosensors. These signal components should be substracted from the output signal to obtain a true output signal which is proportional to signal charges.